1. Technical Field
This disclosure relates to integrated circuits, and more particularly to one-of-n logic circuits.
2. Description of the Related Art
Generally speaking, N-nary logic, which is commonly referred to as N-nary dynamic logic or NDL, refers to a logic family which supports a variety of signal encodings that are of the 1 of n form where n may be any integer greater than one. A more common implementation of NDL uses 1 of four encodings, which uses four wires or signals to indicate one of four possible values.
In the N-nary design style, a 1 of four (or a 1 of n) signal corresponds to a bundle of wires kept together throughout the inter-cell route, which requires the assertion of no more than one wire either while precharging or evaluating. A traditional binary logic design in comparison would use only two wires to indicate four values by asserting neither, one, or both wires together. The number of additional wires represents one difference of the N-nary logic style, and on the surface makes it appear unacceptable for use in microprocessor designs. One-of-n signals are less information efficient than traditional signals because they require at least twice the number of wires, but N-nary signals have the advantage of including signal validation information, which is not possible with traditional signals. It is this additional information (the fact that when zero wires are asserted the result is not yet known) that indirectly allows us to eliminate P-channel logic and all of the series synchronization elements required in traditional designs.
In designs that use the one-of-n encodings, it is sometimes necessary to use a storage element. However, to use a conventional storage element, the one-of-n signal encoding must first be converted to a one of one encoding, which is inefficient. In addition, conventional storage elements are typically clocked devices, which causes additional power consumption.